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CY23EP09
2.5V or 3.3V, 10-220 MHz, Low Jitter, 9-Output Zero Delay Buffer
Features
* 10 MHz to 220 MHz maximum operating range * Zero input-output propagation delay, adjustable by loading on CLKOUT pin * Multiple low-skew outputs -- 45 ps typical output-output skew -- One input drives nine outputs, grouped as 4 + 4 + 1 * 25 ps typical cycle-to-cycle jitter * 15 ps typical period jitter * Standard and High drive strength options * Available in space-saving 16-pin 150-mil SOIC or 4.4-mm TSSOP packages * 3.3V or 2.5V operation * Industrial temperature available
Functional Description
The CY23EP09 is a 2.5V or 3.3V zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin SOIC or TSSOP package. The -1H version operates up to 220 (200) MHz frequencies at 3.3V (2.5V), and has higher drive than the -1 devices. All parts have on-chip PLLs that lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. There are two banks of four outputs each, which can be controlled by the Select inputs as shown in the "Select Input Decoding" table on page 2. If all output clocks are not required, BankB can be three-stated. The select inputs also allow the input clock to be directly applied to the outputs for chip and system testing purposes. The PLL enters a power-down mode when there are no rising edges on the REF input (less than ~2 MHz). In this state, the outputs are three-stated and the PLL is turned off, resulting in less than 25 A of current draw. In the special case when S2:S1 is 1:0, the PLL is bypassed and REF is output from DC to the maximum allowable frequency. The part behaves like a non-zero delay buffer in this mode, and the outputs are not tri-stated. The CY23EP09 is available in different configurations, as shown in the Ordering Information table. The CY23EP09-1 is the base part. The CY23EP09-1H is the high-drive version of the -1, and its rise and fall times are much faster than the -1. These parts are not intended for 5V input-tolerant applications
Block Diagram
PLL
REF CLKOUT CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 Select Input Decoding S1 CLKB2 CLKB3 CLKB4
Pin Configuration
MUX
Top View
REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
S2
Cypress Semiconductor Corporation Document #: 38-07760 Rev. *B
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised October 5, 2005
CY23EP09
Pin Definition
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 REF[1] CLKA1[2] CLKA2[2] VDD GND CLKB1[2] CLKB2 S2[3] S1[3] CLKB3[2] CLKB4[2] GND VDD CLKA3[2] CLKA4[2] CLKOUT[2]
[2]
Signal Input reference frequency Buffered clock output, Bank A Buffered clock output, Bank A 3.3V or 2.5V supply Ground Buffered clock output, Bank B Buffered clock output, Bank B Select input, bit 2 Select input, bit 1 Buffered clock output, Bank B Buffered clock output, Bank B Ground 3.3V or 2.5V supply Buffered clock output, Bank A Buffered clock output, Bank A
Description
Buffered output, internal feedback on this pin
Select Input Decoding
S2 0 0 1 1 S1 0 1 0 1 CLOCK A1-A4 Three-state Driven Driven Driven CLOCK B1-B4 Three-state Three-state Driven Driven CLKOUT[4] Driven Driven Driven Driven Output Source PLL PLL Reference PLL PLL Shutdown N N Y N
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay between the input and output. Since the CLKOUT pin is the internal feedback to the PLL, its relative loading can adjust the input-output delay. The output driving the CLKOUT pin will be driving a total load of 5 pF plus any additional load externally connected to this pin. For applications requiring zero input-output delay, the total load on each output pin (including CLKOUT) must be the same. If input-output delay adjustments are required, the CLKOUT load may be changed to vary the delay between the REF input and remaining outputs. For zero output-output skew, be sure to load all outputs equally. For further information refer to the application note entitled "CY2305 and CY2309 as PCI and SDRAM Buffers".
Notes: 1. Weak pull-down. 2. Weak pull-down on all outputs. 3. Weak pull-ups on these inputs. 4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07760 Rev. *B
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CY23EP09
Absolute Maximum Conditions
Supply Voltage to Ground Potential ................. -0.5V to 4.6V DC Input Voltage...................................... VSS - 0.5V to 4.6V Storage Temperature .................................... -65C to 150C Junction Temperature .................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015.............................. > 2000V Min. 3.0 2.3 0 -40 - - - - - - - - 1-1.5 0.8 29 41 37 41 0.01 95 70 58 48 50 Max. 3.6 2.7 70 85 30 30 22 22 15 15 15 5 Unit V V C C pF pF pF pF pF pF pF pF MHz MHz ms C/W C/W C/W C/W
Operating Conditions
Parameter VDD3.3 VDD2.5 TA CL[5] 3.3V Supply Voltage 2.5V Supply Voltage Operating Temperature (Ambient Temperature)--Commercial Operating Temperature (Ambient Temperature)--Industrial Load Capacitance, <100 MHz, 3.3V Load Capacitance, <100 MHz, 2.5V with High drive Load Capacitance, <133.3 MHz, 3.3V Load Capacitance, <133.3 MHz, 2.5V with High drive Load Capacitance, <133.3 MHz, 2.5V with Standard drive Load Capacitance, >133.3 MHz, 3.3V Load Capacitance, >133.3 MHz, 2.5V with High drive CIN BW ROUT Input Capacitance[6] Closed-loop bandwidth (typical), 3.3V Closed-loop bandwidth (typical), 2.5V Output Impedance (typical), 3.3V High drive Output Impedance (typical), 3.3V Standard drive Output Impedance (typical), 2.5V High drive Output Impedance (typical), 2.5V Standard drive tPU Theta Ja[7] Theta Jc[7] Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) Dissipation, Junction to Ambient, 16-pin SOIC Dissipation, Junction to Ambient, 16-pin TSSOP Dissipation, Junction to Case, 16-pin SOIC Dissipation, Junction to Case, 16-pin TSSOP Description
3.3V DC Electrical Specifications
Parameter VDD VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Supply Voltage Input LOW Voltage Input HIGH Voltage Input Leakage Current Input HIGH Current Output LOW Voltage Output HIGH Voltage 0 < VIN < VIL VIN = VDD IOL = 8 mA (standard drive) IOL = 12 mA (High drive) IOH = -8 mA (standard drive) IOH = -12 mA (High drive) REF = 0 MHz (Industrial) Supply Current Unloaded outputs, 66-MHz REF
Notes: 5. Applies to Test Circuit #1. 6. Applies to both REF Clock and internal feedback path on CLKOUT. 7. Theta Ja, EIA JEDEC 51 test board conditions, 2S2P; Theta Jc Mil-Spec 883E Method 1012.1.
Test Conditions
Min. 3.0 - 2.0 - - - - 2.4 2.4 - - -
Max. 3.6 0.8 VDD+0.3 10 100 0.4 0.4 - - 12 25 30
Unit V V V A A V V V V A A mA
Power Down Supply Current REF = 0 MHz (Commercial)
Document #: 38-07760 Rev. *B
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CY23EP09
2.5V DC Electrical Specifications
Parameter VDD VIL VIH IIL IIH VOL VOH IDD (PD mode) IDD Description Supply Voltage Input LOW Voltage Input HIGH Voltage Input Leakage Current Input HIGH Current Output LOW Voltage Output HIGH Voltage 0Power Down Supply Current REF = 0 MHz (Commercial)
3.3V and 2.5V AC Electrical Specifications
Parameter 1/t1 Description Maximum Frequency[8] (Input/Output) 3.3V High drive 3.3V Standard drive 2.5V High drive 2.5V Standard drive TIDC t2 / t1 t3,t4 Input Duty Cycle Output Duty Cycle[9] Rise, Fall Time (3.3V)[9] <133.3 MHz >133.3 MHz <133.3 MHz >133.3 MHz Std drive, CL = 30 pF, <100 MHz Std drive, CL = 22 pF, <133.3 MHz Std drive, CL = 15 pF, <167 MHz High drive, CL = 30 pF, <100 MHz High drive, CL = 22 pF, <133.3 MHz High drive, CL = 15 pF, >133.3 MHz t3, t4 Rise, Fall Time (2.5V)[9] Std drive, CL = 15 pF, <133.33 MHz High drive, CL = 30 pF, <100 MHz High drive, CL = 22 pF, <133.3 MHz High drive, CL = 15 pF, >133.3 MHz t5 Output to Output Skew [9] All outputs equally loaded, 3.3V supply, 2.5 supply standard drive All outputs equally loaded, 2.5V supply high drive t6 Delay, REF Rising Edge to PLL Bypass mode CLKOUT Rising Edge[9] PLL enabled @ 3.3V PLL enabled @2.5V t7 Part to Part Skew[9] Measured at VDD/2. Any output to any output, 3.3V supply Measured at VDD/2. Any output to any output, 2.5V supply
Notes: 8. For the given maximum loading conditions. See CL in Operating Conditions Table. 9. Parameter is guaranteed by design and characterization. Not 100% tested in production.
Test Conditions
Min. 10 10 10 10 25 40 47 45 - - - - - - - - - - - - 1.5 -100 -200 - -
Typ. - - - - - - - - - - - - - - - - - - 45 - - - - - -
Max. 220 167 200 133 75 60 53 55 1.6 1.6 0.6 1.2 1.2 0.5 1.5 2.1 1.3 1.2 100 110 4.4 100 200 150 300
Unit MHz MHz MHz MHz % % % % ns ns ns ns ns ns ns ns ns ns ps ps ns ps ps ps ps
Document #: 38-07760 Rev. *B
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CY23EP09
3.3V and 2.5V AC Electrical Specifications (continued)
Parameter tLOCK TJCC[9,10] Description PLL Lock Time[9] Test Conditions Stable power supply, valid clocks presented on REF and CLKOUT pins 3.3V supply, >66 MHz, <30 pF, standard drive 3.3V supply, >66 MHz, <30 pF, high drive 2.5V supply, >66 MHz, <15 pF, standard drive 2.5V supply, >66 MHz, <15 pF, high drive 2.5V supply, >66 MHz, <30 pF, high drive S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive S2:S1 = 1:0 mode, 3.3V, <15pF, high drive S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive S2:S1 = 1:0 mode, 2.5V, <15pF, high drive TPER[9,10] Period Jitter, Peak 3.3V supply, 66-100 MHz, <15 pF 3.3V supply, >100 MHz, <15 pF 3.3V supply, >66 MHz, <30 pF, standard drive 3.3V supply, >66 MHz, <30 pF, high drive 2.5V supply, >66 MHz, <15 pF, standard drive 2.5V supply, 66-100 MHz, <15 pF, high drive 2.5V supply, >100 MHz, <15 pF, high drive S2:S1 = 1:0 mode, 3.3V, <15pF, standard drive S2:S1 = 1:0 mode, 3.3V, <15pF, high drive S2:S1 = 1:0 mode, 2.5V, <15pF, standard drive S2:S1 = 1:0 mode, 2.5V, <15pF, high drive Min. - - - - - - - - - - - - - - - - - - - - - - Typ. - 25 65 53 35 30 75 16 14 23 22 20 15 40 30 25 25 15 28 24 40 37 Max. 1.0 55 125 100 95 65 145 - - - - 75 45 100 70 60 60 45 - - - - Unit ms ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps ps
Cycle-to-cycle Jitter, Peak 3.3V supply, >66 MHz, <15 pF
Note: 10. Typical jitter is measured at 3.3V or 2.5V, 29C, with all outputs driven into the maximum specified load. Further information regarding jitter specifications may be found in the application note "Understanding Data Sheet Jitter Specifications for Cypress Clock Products."
Switching Waveforms
Duty Cycle Timing
t1 t2 VDD/2 VDD/2 VDD/2
All Outputs Rise/Fall Time
OUTPUT 2.0V(1.8V) 0.8V(0.6V) t3 2.0V(1.8V) 0.8V(0.6V) t4 3.3V(2.5V) 0V
Document #: 38-07760 Rev. *B
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CY23EP09
Switching Waveforms (continued)
Output-Output Skew
OUTPUT VDD/2
OUTPUT t5
VDD/2
Input-Output Propagation Delay
INPUT VDD/2
CLKOUT t6
VDD/2
Part-Part Skew
Any output, Part 1 or 2 VDD/2
Any output, Part 1 or 2 t7
VDD/2
Test Circuits
Test Circuit # 1 V DD 0.1 F CLK OUTPUTS C LOAD V DD 0.1 F GND GND
Document #: 38-07760 Rev. *B
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CY23EP09
Supplemental Parametric Information
1200 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -1200 -20 -10 0
Delay REF Input to CLKA/B (ps)
S tandard D rive H igh D rive
10
20
Load C LK O U T- Load C LK A/B (pF)
Figure 1. 2.5V Typical Room Temperature Graph for REF Input to CLKA/CLKB Delay versus Loading Difference between CLKOUT and CLKA/CLKB. Data is shown for 66 MHz. Delay is a weak function of frequency.
1200 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 -1200 -20 -10 0
Standard Drive High Drive
10
20
Load CLKOUT- Load CLKA/B (pF)
Figure 2. 3.3V Typical Room Temperature Graph for REF Input to CLKA/CLKB Delay versus Loading Difference between CLKOUT and CLKA/CLKB. Data is shown for 66 MHz. Delay is a weak function of frequency.
Document #: 38-07760 Rev. *B
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CY23EP09
200 175 150 125 100 75 50 25 33 66 100 133 Frequency (MHz) Figure 3. 3.6V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature. Note that the 30-pF data above 100 MHz is beyond the data sheet specification of 22 pF. 166
15pF, -45C, Standard Drive 15pF, 90C, Standard Drive 30pF, -45C, Standard Drive 30pF, 90C, Standard Drive 15pF, -45C, High Drive 15pF, 90C, High Drive 30pF, -45C, High Drive 30pF, 90C, High Drive
200
233
120 100 80 60 40 20 33 66 100 133 Frequency (MHz)
Figure 4. 2.7V Measured Supply Current versus Frequency, Drive Strength, Loading, and Temperature. Note that the 30-pF high-drive data above 100bMHz is beyond the data sheet specification of 22 pF.
15pF, -45C, Standard Drive 15pF, 90C, Standard Drive 15pF, -45C, High Drive 15pF, 90C, High Drive 30pF, -45C, High Drive 30pF, 90C, High Drive
166
200
Document #: 38-07760 Rev. *B
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CY23EP09
350 300 250 200 150 100 50 0 0 50 100 150 200 250 F re q u e n c y (M H z ) 15 15 30 30 pF, pF, pF, pF, S ta n d a rd D riv e H ig h D riv e S ta n d a rd D riv e H ig h D riv e
Figure 5. Typical 3.3V Measured Cycle-to-cycle Jitter at 29C, versus Frequency, Drive Strength, and Loading
350 300 250 200 150 100 50 0 0 20 40 60 80 100 F re q u e n c y (M H z ) 120 140 160 180 200 1 5 p F , S t a n d a r d D r iv e 1 5 p F , H ig h D r iv e 3 0 p F , H ig h D r iv e
Figure 6. Typical 2.5V Measured Cycle-to-cycle Jitter at 29C, versus Frequency, Drive Strength, and Loading
250 15 15 30 30 pF, pF, pF, pF, S t a n d a r d D r iv e H ig h D r iv e S t a n d a r d D r iv e H ig h D r iv e
200
150
100
50
0 0 50 100 F re q u e n c y (M H z ) 150 200 250
Figure 7. Typical 3.3V Measured Period Jitter at 29C, versus Frequency, Drive Strength, and Loading
250 1 5 p F , S t a n d a r d D r iv e 1 5 p F , H ig h D r iv e 3 0 p F , H ig h D r iv e
200
150
100
50
0 0 50 100 F re q u e n c y (M H z ) 150 200 250
Figure 8. Typical 2.5V Measured Period Jitter at 29C, versus Frequency, Drive Strength, and Loading Document #: 38-07760 Rev. *B Page 9 of 13
CY23EP09
-90 SSB Phase Noise (dBc/Hz) -100 -110 -120 -130
2.5V, Standard Drive 2.5V, High Drive 3.3V, Standard Drive 3.3V, High Drive
2.5V, Standard Drive 2.5V, High Drive 100 MHz
-140 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 Offset Frequency (Hz) 1.E+06 1.E+07 1.E+08
-90 SSB Phase Noise (dBc/Hz) -100 -110 -120 -130
2.5V, High Drive 3.3V, High Drive
3.3V, Standard Drive 2.5V, Standard Drive
156.25 MHz
-140 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 Offset Frequency (Hz) 1.E+06 1.E+07 1.E+08
Figure 9. Typical Phase-noise Data at 100 MHz (top) and 156.25 MHz (bottom) across VDD and Drive Strength[10]
Document #: 38-07760 Rev. *B
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CY23EP09
Ordering Information
Ordering Code Lead-free CY23EP09SXC-1 CY23EP09SXC-1T CY23EP09SXI-1 CY23EP09SXI-1T CY23EP09SXC-1H CY23EP09SXC-1HT CY23EP09SXI-1H CY23EP09SXI-1HT CY23EP09ZXC-1H CY23EP09ZXC-1HT CY23EP09ZXI-1H CY23EP09ZXI-1HT 16-pin 150-mil SOIC 16-pin 150-mil SOIC - Tape and Reel 16-pin 150-mil SOIC - 16-pin 150-mil SOIC - Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC - Tape and Reel 16-pin 150-mil SOIC 16-pin 150-mil SOIC - Tape and Reel 16-pin 4.4-mm TSSOP 16-pin 4.4-mm TSSOP - Tape and Reel 16-pin 4.4-mm TSSOP 16-pin 4.4-mm TSSOP - Tape and Reel Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Commercial Commercial Industrial Industrial Package Type Operating Range
Package Drawing and Dimensions 16 Lead (150 Mil) SOIC
8 1
16-Lead (150-Mil) SOIC S16
PIN 1 ID
DIMENSIONS IN INCHES[MM] MIN. MAX. REFERENCE JEDEC MS-012
0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197]
PACKAGE WEIGHT 0.15gms
PART # S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG. 9 16
0.386[9.804] 0.393[9.982]
SEATING PLANE
0.010[0.254] 0.016[0.406]
X 45
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] BSC 0.0138[0.350] 0.0192[0.487] 0.004[0.102] 0.0098[0.249]
0~8
0.016[0.406] 0.035[0.889]
0.0075[0.190] 0.0098[0.249]
51-85068-*B
Document #: 38-07760 Rev. *B
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CY23EP09
Package Drawing and Dimensions (continued)
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
PACKAGE WEIGHT 0.05 gms PART # Z16.173 STANDARD PKG. ZZ16.173 LEAD FREE PKG.
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027]
51-85091-*A
4.90[0.193] 5.10[0.200]
0.09[[0.003] 0.20[0.008]
All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-07760 Rev. *B
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(c) Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
CY23EP09
Document History Page
Document Title: CY23EP09 2.5V or 3.3V, 10-220-MHz, Low Jitter, 9-Output Zero Delay Buffer Document Number: 38-07760 REV. ** *A *B ECN NO. 345446 355777 401036 Issue Date See ECN See ECN See ECN Orig. of Change RGL RGL RGL New data sheet Updated part to part skew to agree with latest char results Added PLL-bypass jitter Added Phase-noise graph Added 2.5V Delay vs. Load graph Removed Preliminary Description of Change
Document #: 38-07760 Rev. *B
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